The 2021 guide categorizes paths to help users understand what the tool is checking:
By 2021, Synopsys encouraged a shift towards for advanced nodes, offering tighter integration between synthesis and implementation. However, the foundational optimization principles from Design Compiler remain relevant. Optimization Phases synopsys timing constraints and optimization user guide 2021
: Added to the required hold time, forcing the tool to insert extra delay if paths are too fast. Clock Transition and Latency The 2021 guide categorizes paths to help users
# Relax setup check to 3 clock cycles set_multicycle_path 3 -setup -from [get_pins reg_a/CP] -to [get_pins reg_b/D] # Adjust hold check accordingly (usually N-1 cycles) set_multicycle_path 2 -hold -from [get_pins reg_a/CP] -to [get_pins reg_b/D] Use code with caution. Asynchronous Clock Groups ( set_clock_groups ) synopsys timing constraints and optimization user guide 2021
2. The 2021 Optimization Flow: Design Compiler to Fusion Compiler